Plasma immersion ion implantation is performed by generating a plasma containing ions of species to be implanted in a semiconductor wafer or workpiece. The plasma may be generated using a plasma source such as a toroidal plasma source at the reactor chamber ceiling. Ion energy sufficient to achieve a desired ion implantation depth profile below the wafer surface is provided by coupling a very high RF bias voltage (e.g., 10 kV to 20 kV) to the semiconductor wafer through an insulated cathode electrode within the wafer support pedestal. High implant dose rate requires a high plasma ion density, which is achieved using a toroidal plasma source operating at a low chamber pressure. The requisite ion implant depth profile requires a very high ion energy, which is achieved by applying a very high RF bias voltage across the plasma sheath at the wafer surface. The process gas employed in plasma immersion ion implantation can be a fluoride or a hydride of the dopant species to be implanted.
In DRAM/flash memory fabrication, it is necessary to implant a semiconductor dopant species into the polycrystalline silicon (polysilicon) gate electrodes to increase their conductivity. The gate electrodes are formed by depositing amorphous silicon on a thin gate oxide layer and then annealing the wafer sufficiently to transform the deposited silicon from the amorphous state to a polycrystalline state. The polycrystalline silicon gate layer thus formed is about 50 nm to 80 nm thick. The implanted species is one that promotes p-type semiconductivity in silicon, such as boron, or n-type semiconductivity, such as arsenic, phosphorous or antimony. There is a need to avoid sputtering of the polycrystalline silicon gate material during the plasma immersion ion implantation. Specifically, it is desirable to minimize sputtering-induced reduction in the gate thickness to less than 10% of initial gate thickness (e.g., not more than a 5 nm to 8 nm loss in gate thickness) during the entire plasma immersion ion implantation process. The plasma immersion ion implantation process must be carried out for a sufficient time to attain a required ion implant dosage in the polysilicon gate layer, corresponding to an electrical resistivity in the range of 100-2000 Ohm/sq.
There is a further need to maintain a stable plasma to minimize plasma impedance fluctuations that would cause fluctuations in the delivered RF bias power or RF bias voltage across the plasma sheath and fluctuations in the delivered RF source power of the toroidal source. Otherwise, fluctuations in the delivered RF bias power will degrade control over ion implantation depth profile, while fluctuations in delivered RF source power will degrade control over ion implant dosage or dose rate. Currently, certain plasma immersion ion implantation processes experience frequent sporadic fluctuations in plasma impedance on the order of 100%. There is a need to reduce such fluctuations.
There is a need to reduce the deposition of solid particles on the wafer surface during plasma immersion ion implantation. Such particle deposition can occur due to (for example) accumulation of plasma by-products as a film on the chamber interior surfaces, such a film being liable to flaking from the sputtering action of the plasma. Currently, for example, certain plasma immersion ion implantation processes tend to accumulate between about 500 and 5000 particles of diameters of at least 0.12 microns on a 300 mm diameter wafer during ion implantation doping of polysilicon gates of flash memories. There is a need to reduce this particle deposition by an order of magnitude, e.g., to a range between about 5 and 50 particles of at least 0.12 microns.